Zhang Jiabin 中文

Zhang Jiabin · 章佳斌

Designing quieter circuits.

Analog · ML · Backscatter

PhD Candidate · Analog IC · Zhejiang University · Low-power analog and mixed-signal IC design

See projects

About

Research

I design ultra-low-power analog front-ends and backscatter transceivers, and build ML-assisted tooling for analog circuit sizing. I work in Prof. Xiaopeng Yu's lab at the Institute of VLSI Design, Zhejiang University, on TSMC55 and SMIC65 processes.

48 %

In-spec rate

analog-sizing-ml · BO convergence

12.1 bit

ENOB

NS-SAR ADC · KAN-calibrated

2 nodes

TSMC 55nm · SMIC 65nm

Active tape-out work

5 blocks

MPW1 modules

WuRx / BGR / GFSK / EH / TopBias

Work

Featured Projects

2026 – present

BackScatter — Backscatter Communications IC

Autonomously integrate a BLE-compatible backscatter sensor SoC in TSMC 55nm ULP technology, enabling smartphones to directly read sensor data without separate gateway hardware.

  • backscatter communications
  • BLE
  • ULP SoC
  • TSMC 55nm
  • sensor

2025 – present

analog-sizing-ml

Open-source analog circuit sizing tool based on BoTorch qEHVI multi-objective Bayesian optimization, supporting gm/Id physical prior warm-start, non-invasive YAML integration with existing Spectre flows.

  • Bayesian optimization
  • qEHVI
  • gm/Id
  • analog sizing
  • EDA automation

2024 – present

KAN Calibration for NS-SAR ADC

Use Kolmogorov–Arnold Networks (KAN) to replace traditional LMS/Volterra calibration of noise-shaping SAR ADC nonlinear mismatch, achieving 12-bit effective resolution in behavioral-level modeling.

  • NS-SAR ADC
  • KAN
  • digital calibration
  • data converters

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Publications

Recent Publications

Publication list coming soon.

Full list →

Contact

Get in touch

Happy to talk about analog IC design, low-power systems, or ML-assisted EDA.