Background
Backscatter communication modulates antenna reflection coefficients to “piggyback” sensor data onto ambient RF signals, consuming almost zero transmit power—a key pathway for IoT nodes to break free from batteries. Recent years have seen µW-scale backscatter sensor nodes demonstrated by UMich, University of Washington, and ZJU teams. The critical step toward consumer-grade ecosystem adoption is compatibility with commercial communication standards (BLE / Wi-Fi).
This project aims to build a complete BLE-compatible backscatter sensor SoC from scratch in TSMC 55nm ULP: RF-powered entire chip, on-chip sensors collect environmental quantities, link-layer frames BLE-compliant broadcast packets decodable directly by COTS smartphone BLE applications. The research direction has no existing IP reserves in the laboratory, with the entire chip completed independently by a single engineer from architecture definition, circuit design, behavioral modeling, to silicon-golden RTL verification across the full chain.
Methodology / Architecture
The first MPW adopts a “broad SoC + duty-cycling” approach: always-on links (Wake-up Receiver, Bandgap, Top Bias Mirror, LDO, Energy Harvester, clock reference) continuously operate to monitor wake-up events, while the remaining sampling and transmission chains duty-cycle at second-scale advertisement periods. Active power matches the harvester’s available output capability under −10 dBm input.
The signal chain is organized as follows: antenna receives 2.4 GHz RF excitation, Energy Harvester rectifier generates DC regulated via V_STORE storage and shunt clamp, LDO and Bandgap output dual voltage rails and references; Wake-up Receiver + Envelope Detector monitor low-duty-cycle wake packets; commercial 26 MHz crystal oscillator + on-chip Pierce driver and Clock Recovery provide system clock and BLE bit-clock; variable-rate SAR ADC and Sensor Frontend digitize temperature and other sensed quantities; BLE link-layer framer completes packet encapsulation (including CRC-24), Backscatter Modulator shapes GFSK-compliant BLE-compatible envelope through antenna impedance modulation.
To ensure silicon success rate, the project established a complete engineering closed-loop: self-built TSMC 55nm gm/Id design library, unified PVT/MC simulation and parallel scheduling templates, BoTorch-based multi-objective sizing optimizer (with gm/Id warm-start prior), and bit-exact digital sign-off with dual-track RTL and floating-point BLE reference models.
Current Progress
- Analog building blocks: Bandgap, TopBiasMirror, PowerSupply/LDO, Wake-up Receiver, INV/NAND/NOR digital std cells characterization completed schematic and PVT verification
- Energy Harvester: completed hand-calculated design + behavioral-level Stage 2 simulation, three-corner output current has ample margin across loads, V_STORE shunt clamp sub-block defined
- Digital baseband (GFSK draft): silicon-golden Python oracle and RTL integer chain achieve bit-exact consistency, floating-point BLE reference model likewise 100% hit; multi-round independent review passed tape-out conditional acceptance
- Clock chain: commercial 26 MHz oscillator + on-chip Pierce driver + Clock Recovery topology selected, PMU–clock joint budget closed
- Engineering infrastructure: gm/Id library v1 (72 tables), ML sizing pipeline, Spectre remote parallelization template, and silicon-golden dual-track sign-off all in production
Next Steps
- Complete SAR ADC + Sensor Frontend sub-block schematic and multi-corner verification, closing system-level integration simulation
- After full commercial flow (synthesis / place & route / STA) for digital std cells, feed back to GLS and timing sign-off
- Block-level and top-level layout, focusing on top-level DRC / LVS / PEX and post-layout critical corner re-runs
- First MPW tape-out package preparation, end-to-end backscatter broadcast demo with smartphone COTS BLE application upon silicon return